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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-31102-1E
ASSP for Graphics Control
Graphics Display Controller MB86291A
s DESCRIPTION
The MB86291A is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car navigation system or amusement equipment. The MB86291A is a graphics display controller with a geometry processor, digital video capture facility, and on-chip SDRAM. Embedding SDRAM implements data transfer at a higher bandwidth, resulting in faster drawing. Integrating the geometry processor reduces the CPU load, thereby improving the performance of the entire system.
s FEATUERS
* Operating frequency : 100 MHz (External clock of 14.32 MHz Max) * Geometry processor: Capable of executing operations for geometric transformation and surface front/rear evaluation. * Memory block: Embedded 16-Mbit SDRAM * Video capture block: Embedded facility to capture digital video images, for example, from TV, capable of easily implementing "Picture in Picture" and video graphics superimposing. * Host interface: Enables direct connection to various CPUs (Fujitsu SparcLite, Hitachi SH3/4 or NEC V83x) . (Continued)
s PACKAGE
208-pin plastic QFP
(FPT-208P-M04)
MB86291A
(Continued) * Drawing features: * Drawing at a peak rate of 800 Mpixels per second (at an internal operating frequency of 100 MHz) * 2D drawing functions: Point, line, triangle, polygon, BLT, and pattern drawing * 3D drawing functions: Point, line, and triangle drawing, and hidden surface removal by Z-buffering * Special effects: Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture mapping (bilinear filtering, perspective correct) , and tiling * Display features : * Maximum display resolution supported : 1024x768 pixels * Color display either with a color palette of 8 bits per pixel or directly using 5-bit RGB colors of 16 bits per pixel * Overlaying four layers of screen, of which two lower layers can be divided into the left and right parts * Supporting two 64x64-pixel hardware cursors * Output of analog RGB and digital RGB signals * Capable of superimposing using an external synchronization mode * Power-supply voltage : Two power supplies at 2.5 V0.2 V for internal circuits and SDRAM, and 3.3 V0.2 V for I/O parts * Package: Plastic QFP with 208 pins (with a lead pitch of 0.5 mm) * Process technology : 0.25 m CMOS
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MB86291A
s PIN ASSIGNMENT
(TOP VIEW)
VSS GV HSYNC VSYNC CSYNC VSS DCLKO VDDE VI7 VI6 VI5 VI4 VI3 VI2 VI1 VI0 VDDI VSS DCLKI EO RESERVE RESERVE RESERVE RESERVE RESERVE TESTH5 CCLK VDDE VSS A24 A23 A22 A21 A20 A19 A18 A17 A16 VDDI VSS A15 A14 A13 A12 A11 A10 A9 A8 TESTL1 VDDE VDDI VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VSS VCC0 R0 R1 VCC1 VSS R2 R3 R4 R5 R6 R7 VCC2 VDDE VSS VCC3 VDDI G0 G1 G2 G3 VSS G4 G5 G6 G7 VDDE B0 B1 B2 B3 VSS B4 B5 B6 B7 VCC4 VDDI VSS VCC5 VDDE CLKSEL0 CLKSEL1 RESET MODE0 MODE1 VSS VCC6 MODE2 TESTL0 VCC7 VSS
ACOMPR VREF VRO AVD3 AOUTR AVS3 AVS2 AVD2 AVS1 AOUTG AVD1 ACOMPG AVS0 AOUTB AVD0 ACOMPB VSS VDDI A7 A6 A5 A4 A3 A2 VDDI VSS PLLVSS S OSCOUT PLLVDD VDDE VSS CLK OSCCNT VSS VDDI WE3 WE2 WE1 WE0 RD BS CS BCLKI VDDI VSS VDDE OPEN DTACK/TC DRACK/DMAAK CKM TESTH4
: Ground VSS/AVS/PLLVSS : 3.3 V power supply VDDH/VDDE VDDL/AVD/PLLVDD/VCC/VDDI : 2.5 V power supply : Analog power supply AVD : PLL power supply PLLVDD : Internal DRAM power supply VCC : Do not connect anything. OPEN : Input the low level. TESTL0/TESTL1 : Input the high level. TESTH0 ~ TESTH5 : Input the high level. RESERVE Notes : * The AVD and PLLVDD should be separated on the board. * Insert a bypass capacitor with a superior high-frequency characteristic between the power supply and ground. Place the capacitor as near the pins as possible.
TESTH0 VSS VDDI D0 D1 D2 D3 D4 D5 D6 D7 VDDE VSS D8 D9 D10 D11 D12 D13 D14 VDDI VSS D15 D16 D17 D18 VDDE D19 D20 D21 D22 D23 D24 VSS VDDI D25 D26 D27 D28 D29 VSS VDDE D30 D31 RDY DREQ INT VSS VDDI TESTH1 TESTH2 TESTH3
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MB86291A
s PIN DESCRIPTION
D0-D31 A2-A24 BCLKI RESET CS RD
DCLKO DCLKI AOUTR, AOUTG, AOUTB HSYNC VSYNC CSYNC EO GV MB86291A Graphics Controller VREF VRO ACOMPR, ACOMPG, ACOMPB R0-R7 G0-G7 B0-B7
Host CPU interface
WE0-WE3 RDY BS DREQ DRACK DTACK INT MODE0MODE2 TESTL, TESTH HQFP208
Vide output interface
CCLK CLK S VI0-VI7
Vide capture interface
Clock
CKM CLKSEL0CLKSEL1 OSCOUT OSCCNT
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MB86291A
* Host Interface Pins Pin Name Input/output MODE0 to MODE2 RESET D0 to D31 A2 to A24 BCLKI BS CS RD WE0 WE1 WE2 WE3 RDY DREQ DRACK/DMAAK DTACK/TC INT TEST0, TEST1, TESTH0 to TESTH5 Input Input Input/output Input Input Input Input Input Input Input Input Input Output Tristate Output Input Input Output Input Hardware reset Host CPU bus data Host CPU bus address (Connect A[24] to MWR in V832 mode.) Host CPU bus clock Bus cycle start signal Chip select signal Read strobe signal D0 to D7 write strobe signal D8 to D15 write strobe signal D16 to D23 write strobe signal D24 to D31 write strobe signal Wait request signal ("0" for wait state with SH3; "1" for wait state with SH4, V832, or SPARClite) DMA request signal (active low with both SH and V832) DMA request acknowledge signal (Connect this to DMAAK in V832 mode. Active high with both SH and V832.) DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high, V832 = active low) Host CPU interrupt signal (SH = active low, V832 = active high) Test signal
Function Host CPU mode/Ready mode select
Note : The host interface can connect the MB86291A to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using the SRAM interface allows the MB86291A to use another CPU.) The host CPU is set by the MODE0 and MODE1 pins as shown below. MODE1 pin L L H H MODE0 pin L H L H SH3 SH4 V832 SPARClite CPU Type
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To use the MODE2 signal at "H" level, set the software setting to two cycles. MODE2 pin L H Ready signal mode Set RDY signal to "Not Ready" level upon completion of bus cycle. Set RDY signal to "Ready" level upon completion of bus cycle.
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MB86291A
Notes : * The host interface transfers data signals at a fixed width of 32 bits. * There are 23 lines for address signals handled in double words ( = 32 bits) and 32 Mbytes of address space. * The external bus can be used at an operating frequency of 100 MHz maximum. * The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output. * The host interface supports DMA transfer using an external DMA controller. * The host interface generates a host processor interrupt signal. * The RESET pin requires low level input of at least 300 s after setting "S" (PLL reset signal) to high level. * Fix the TEST signal at high level. * In the V832 mode, connect the following pins as specified : SCARLET Pin Name A24 DTACK DRACK * Vide Output Interface Pin Name Input/output DCLKO DCLKI HSYNC VSYNC CSYNC EO GV R0-R7 G0-G7 B0-B7 AOUTR AOUTG AOUTB VREF ACOMPR ACOMPG ACOMPB VRO Output Input Input/output Input/output Output Input Output Output Output Output Display dot clock signal output Dot clock signal input Horizontal sync signal output Horizontal sync signal input in external synchronization mode Vertical sync signal output Vertical sync signal input in external synchronization mode Composite sync signal output Even/odd-number field identification input Graphics/video select signal Digital video (R) signal output Digital video (G) signal output Digital video (B) signal output V832 Signal Name MWR TC DMAAK
Function
Analog output Analog video (R) signal output Analog output Analog video (G) signal output Analog output Analog video (B) signal output Analog Analog Analog Analog Analog Reference voltage input pin R-signal compensation pin G-signal compensation pin B-signal compensation pin Reference current setting pin
Notes : * The video output interface contains an 8-bit D/A converter to output analog RGB signals. Also, the eight-bit RGB digital output pins can connect an external digital video encoder. * Using an additional external circuit, the video output interface can generate composite video signals. * The video output interface can provide display synchronized with external video. The mode for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set dot clock as for normal display. 6
MB86291A
* The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset. * Terminate the AOUTR, AOUTG, and AOUTB pins with a resistance of 75 . * Input 1.1 V to the VREF pin. Between this pin and analog ground, insert a bypass capacitor (one with a superior high-frequency characteristic such as a laminated ceramic capacitor). * Connect the ACOMPR, ACOMPG, and ACOMPB pins to the 0.1 F ceramic capacitor ahead of the analog power supply. * Connect the VRO pin to the analog ground with a 2.7 k resistor. * For noninterlaced display in external synchronization mode, input "0" to the EO pin, for example, using a pull-down resistor. * The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level signal to select video.
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MB86291A
* Video Capture Interface Pin Name Input/output CCLK VI0-VI7 Input Input Digital video data input
Function Digital video input clock signal input
Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format. * Clock Input Pin Name CLK S CKM CLKSEL1, CLKSEL0 OSCOUT* OSCCNT*
1 2
Input/output Input Input Input Input Input/output Input Clock input signal PLL reset signal Clock mode signal Clock rate select signal
Function
For connection of crystal oscillator (Reserved) For selection of crystal oscillator (Reserved)
*1 : Do not connect anything. *2 : Input the "H" level. Notes : * The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal operating clock and display dot clock. Usually input 4 Fsc ( = 14.31818 MHz) . The internal PLL generates the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz. * The internal operating clock signal to be used can be selected between the clock signal (100 MHz) generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI input to use the host CPU bus at 100 MHz. CKM Clock Mode L H Select internal PLL output. Select host CPU bus clock (BCLKI)
Note : Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM = L. CLKSEL1 CLKSEL0 Clock Frequency L L H H L H L H Input 13.5 MHz. Input 14.32 MHz. Input 17.73 MHz. Reserved
Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300 s or more
8
MB86291A
s BLOCK DIAGRAM
D0-D31 Host Interface A2-A24
External Video Interface Controller
RBT656
Display Controller DAC Memory Interface Controller
DRGB
ARGB
Geometry Engine
2D/3D Rendering Engine
Embedded SDRAM
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MB86291A
s FUNCTION BLOCKS
* Host Interfacee This block allows the MB86291A to be connected to the SH3 or SH4 microprocessor from Hitachi Ltd., the V83x microprocessor from NEC, or to the SPARCLite from Fujitsu without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to this device's graphics memory or internal register using the external DMA controller. * Memory Interface Controller and Embedded SDRAM The embedded 16-megabit SDRAM eliminates the need for external memory. The SDRAM operates at 100 MHz. * Display Controller This block contains a three-channel, eight-bit D-A converter to output analog RGB signals. The block has eightbit RGB digital video outputs, allowing an external digital video encoder to be connected. The block supports resolutions of up to XGA (1024x768 pixels), enabling flexible setting. * External Video Interface Controller This block can input digital video in the ITU RBT-656 format by connecting an external digital video decoder using the eight-bit video input pin. Input video data is stored temporarily in graphics memory and then displayed on the screen in synchronization with the display scan. The block supports video in the NTSC and PAL formats. * Set-up Engine The on-chip geometry engine executes mathematical operations required for graphics processing precisely using the fronting-point format. The geometry engine executes the required geometry processes selected depending on the drawing mode and primitive type settings up to the final drawing process. * 2D/3D Rendering Engine This block draws images in two or three dimensions. * 2D drawing The block provides the anti-aliasing and alpha blending functions to display high-quality images even on a lowresolution LCD. * 3D drawing The block provides true 3D drawing functions such as perspective texture mapping and Gouraud shading.
10
MB86291A
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output current Power pin current Ambient operating temperature Ambient storage temperature Symbol VDDL*1 VDDH VI IO IPOW TA Tstg Rating Min - 0.5 - 0.5 - 0.5 - 13 0 - 30* - 55
2
Max + 3.0 + 4.0 VDDH + 0.5 (< 4.0) + 13 60 + 70 + 85*2 + 125
Unit V V mA mA C C
*1 : The analog and PLL power supplies are included. *2 : Model supporting a wider range of temperatures WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITION
Parameter Power supply voltage Input voltage (High level) Input voltage (Low level) VREF pin input voltage VRO pin external resistor AOUT pin external resistor*2 ACOMP pin external capacitor* Ambient operating temperature
3
Symbol VDDL*1 VDDH VIH VIL VREF RVRO RAOUT CACOMP TA
Value Min 2.3 3.0 2.0 - 0.3 1.05 - 40 Typ 2.5 3.3 1.10 2.7 75 0.1 Max 2.7 3.6 VDDH + 0.3 + 0.8 1.15 + 85
Unit V V V V V k F C
*1 : The analog and PLL power supplies are included. *2 : AOUTR, AOUTG and AOUTB pins *3 : ACOMPR, ACOMPG, and ACOMPB pins
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MB86291A
Notes : * The VDDL and VDDH power supplies can be turned on or off in either order. Note, however, that the VDDH voltage must not be applied alone continuously for several seconds. * After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set the S pin to high level and input the RESET signal held at low level for at least 300 s. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
12
MB86291A
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Output voltage (High level) *1 Output voltage (Low level) *2 Output current (High level) Output current (Low level) AOUT output current*5 AOUT voltage*6 Input leakage current Pin capacitance Full scale Zero scale VDDL = 2.5 V 0.2 V, VDDH = 3.3 V 0.3, VSS = 0.0 V, TA = 0 C to + 70 C Value Symbol Unit Min Typ Max VOH VOL IOHM* IOHH*
4 3
VDDH - 0.2 0.0 - 4.0 - 8.0 4.0 8.0 9.90 0 - 0.1
10.42 2
VDDH 0.2 10.94 20 + 1.1 5 16
V V mA mA mA A V A pF
IOLM*4 IOLH*3 IAOUT VAOUT IL C
*1 : Value when -100 A current flows into output pins. *2 : Value when 100 A current flows into output pins. *3 : Output characteristics of INT, DREQ, and RDY *4 : Output characteristics of the signals (excluding analog signals) other than those in *3 *5 : AOUTR, AOUTG, and AOUTB pin output current. Condition VREF = 1.10 V, RVRO = 2.7 k (The full-scale output current calculation expression is (VREF / RVRO) x 25.575) *6 : AOUTR, AOUTG, and AOUTB pins
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MB86291A
2. AC Characteristics
* Input measurement conditions
(VIH = 2.0 V, VIL = 0.8 V)
tr VIH
tf
Input
80% (VIH + VIL) / 2 20% VIL
80%
20%
*tr, tf 5 ns *Input measurement standard : (VIH + VIL) / 2
* Output measurement conditions
VIH
Input
VIL tpHL, tpZL VOH
(VIH + VIL) /2
tpLH, tpZH
Output 1
VOL
VDD/2
VDD/2
tpLZ
Output 2
0.5 V VOL
tpHZ VOH
Output 3
0.5 V
*Output measurement standard : tpLZ : VOL + 0.5 V tpHZ : VOH - 0.5 V Else : VDD/2 14
MB86291A
(1) Host Interface * Clock signals Parameter BCLKI frequency BCLKI H period BCLKI L period * Host interface signals (External load of 20 pF) Parameter Address setup time Address hold time BS setup time BS hold time CS setup time CS hold time RD setup time RD hold time WE setup time WE hold time Write data setup time Write data hold time DTACK setup time DTACK hold time DRACK setup time DRACK hold time Read data delay time (to RD) Read data delay time RDY delay time (to CS) RDY delay time INT delay time DREQ delay time MODE hold time *1 : Hold time for reset cancellation *2 : Read data is output one cycle before the CPU samples it. Symbol tADS tADH tBSS tBSH tCSS tCSH tRDS tRDH tWES tWEH tWDS tWDH tDAKS tDAKH tDRKS tDRKH tRDDZ tRDD tRDYDZ tRDYD tINTD tDRQD tMODH Condition *2 *1 Value Min 4 0 3 0 3 0 3 0 5 1 3 0 3 0 3 0 3.0 4.5 2.5 2.5 3.0 2.5 Typ Max 11.0 10.5 5.0 6.0 6.5 6.0 20.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol fBCLKI tHBCLKI tLBCLKI Condition Value Min 1 1 Typ Max 100 Unit MHz ns ns
15
MB86291A
* Clock
1/fBCLKI tHBCLKI tLBCLKI
BCLKI
* Input setup and hold times
BCLKI
A2~A24, BS, CS, DTACK, DRACK
tADS, tBSS, tCSS, tDAKS, tDRKS tADH, tBSH, tCSH, tDAKH, tDRKH
* Read/write enable (RD, WE) and input data (D) setup times
BCLKI
BS
RD, WE
tRDS, tWES
tRDH, tWEH
D0~D31
tWDS
tWDH
16
MB86291A
* DREQ output delay time
BCLKI
DREQ (output)
tDRQD
* INT output delay time
BCLKI
INT (output)
tINTD
* RDY delay value (with respect to CS)
BCLKI
CS
High-Z RDY (output)
tRDYDZ tRDYDZ
High-Z
17
MB86291A
* RDY/D output delay values
BCLKI
RD
tRDD tRDDZ
D0~D31 (output)
Output data
High-Z
RDY
tRDYD tRDYD
* MODE signal hold time
RESET
MODE0~ MODE2
tMODH
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MB86291A
(2) Video Interface * Clock Parameter CLK frequency CLK H period CLK L period DCLKI frequency DCLKI H period DCLKI L period DCLKO frequency * Input signals Parameter HSYNC input pulse width HSYNC input setup time HSYNC input hold time VSYNC input pulse width EO input setup time EO input hold time Symbol tWHSYNC0 tWHSYNC1 tSHSYNC tHHSYNC tWHSYNC1 tSEO tHEO Condition *1 *2 *2 *2 *3 *3 Value Min 3 3 10 10 1 10 10 Typ Max unit clock clock ns ns HSYNC 1 cycle ns ns Symbol fCLK tHCLK tLCLK fDCLKI tHDCLKI tLDCLKI fDCLKO Condition Value Min 25 25 5 5 Typ 14.32 Max 67 67 unit MHz ns ns MHz ns ns MHz
*1 : Applied only in PLL synchronization mode (CKS = 0) . The reference clock is the internal PLL's output with Cycle = 1/ (14 fCLK) . *2 : Applied only in DCLKI synchronization mode (CKS = 1) . The reference clock is DCLKI. *3 : Based on the edge with VSYNC negated. * Output signals Parameter EO output delay time HSYNC output delay time VSYNC output delay time CSYNC output delay time GV output delay time Symbol tDEO tDHSYNC tDVSYNC tDCSYNC tDGV Condition * Value Min 1.5 1.5 1.5 1.5 1.5 Typ Max 11 11 11 11 11 unit ns ns ns ns ns
* : The EO output varies at the same time as VSYNC is asserted.
19
MB86291A
* Clock
1/fCLK tHCLK tLCLK
CLK
VIH VIL
* HSYNC signal setup and hold
1/fDCLKI tHDCLKI tLDCLKI
DCLKI
HSYNC (input)
tSHSYNC tHHSYNC
* EO signal setup and hold
VSYNC
EO (input)
tSEO tHEO
* Output signal delay
DCLKO
EO (output) HSYNC (output) VSYNC (output) CSYNC GV
tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV
20
MB86291A
(3) Video Capture Interface * Clock Parameter CCLKI frequency CCLKI H period CCLKI L period * Input signals Parameter VI setup time (External load of 25 pF) VI hold time (External load of 15 pF) * Clock
1/fCLK tHCLK tLCLK
Symbol fCCLKI tHCCLKI tLCCLKI
Condition
Value Min 1 1 Typ 27 Max
unit MHz ns ns
Symbol tVIS tVIH
Condition
Value Min 11 2 Typ Max
unit ns ns
CLK
VIH VIL
* Video input
CCLKI
VI0~VI7
tVIS
tVIH
21
MB86291A
(4) PLL Standards Parameter Input frequency Output frequency Duty ratio Jitter Value Min 93.1 - 150 Typ 14.31818 Max 200.45452 101.3 + 180 Unit MHz MHz % ps Multiplied by 14 PLL output clock H/L pulse width ratio Cycle difference between two consecutive cycles Remarks
22
MB86291A
s ORDERING INFORMATION
Part Number MB86291APFVS Package 208-pin plastic QFP (FPT-208P-M04) Remarks
23
MB86291A
s PACKAGE DIMENSION
208-pin plastic QFP (FPT-208P-M04) Note : Pins width and pins thickness include plating thickness.
30.600.20(1.205.008)SQ 28.000.10(1.102.004)SQ
156 105
0.17 -0.08 .007 -.003
104
+0.03 +.001
157
0.08(.003)
Details of "A" part 3.75 -0.30 .148 -.012
+0.20 +.008
(Mounting height)
0.40 -0.15 INDEX 0~8
53
+0.10 +.004
.016 -.006 (Stand off)
208
"A"
LEAD No.
1
52
0.50(.020)
0.220.05 (.009.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.08(.003)
M
C
2000 FUJITSU LIMITED F208020S-c-2-3
Dimension in mm (inches)
24
MB86291A
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0203 (c) FUJITSU LIMITED Printed in Japan

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